1. Field of the Invention
The present invention relates to a method of erasing a flash EPROM or EEPROM (electrically erasable programmable read-only memory) and, more particularly, to an erasing method which repeats erase and verification after executing a pre-erase dummy writing operation with respect to entire memory cells to be erased. The invention further relates to the structure of a memory and a reprogramming method thereof adapted for preventing deterioration of gate oxide films that may be derived from repeated reprogramming actions.
2. Description of the Related Art
In flash EEPROMs, there occurs a phenomenon that threshold voltages thereof are widely distributed after erasing in an ordinary batch erasing mode due to variations of the capacitive coupling ratio between sources and floating gates in individual cells, so that problems are raised as a result inclusive of overerase where the threshold voltage is rendered negative, and in some partial cells on the chip, the threshold voltage is increased in excess to consequently cause improper operation.
It is generally known that, particularly when any overerased cell is existent in the chip, such a condition causes a fatal defect on the entire operation of the device. More specifically, in reading one cell on a bit line where any overerased cell is existent, a current comes to flow via such overerased cell, so that the cell in its off-state (written state) is decided erroneously to be in an on-state.
In erasing a flash EEPROM, it has been customary heretofore to execute the procedure of first pre-erase writing (dummy writing "0") every memory cell in the sector to be erased, then erasing the cells little by little while repeating erasure and verification, and completing the erasing operation after the threshold voltage Vth is lowered below a predetermined decision value.
However, according to such conventional erasing method that erases the cells gradually while repeating erasure and verification, there occurs a fault that, due to some variations of the gate film thickness in the chip, the threshold value is rendered negative in any memory cell transistor having a great threshold shift derived from the erasing operation, whereby such cell is overerased. And in conformity with an increase of the frequency of reprogramming operations, the threshold voltage distribution is spread as shown in FIG. 1 to eventually increase the possibility of overerasing. If the threshold voltage for deciding the erase is set to be high in an attempt to avert such a problem of overerasing, the driving capability of the transistor is lowered to consequently prolong the data reading time, or the supply voltage fails to be sufficient for a normal operation at any level below the threshold voltage for deciding the erase, thereby inducing an impediment to the latest requirements for realizing a lower rated supply voltage.
Further considering a memory chip where data are reprogrammed so many times, it is prone to occur that the reprogramming is concentrated merely on a specific portion of the chip to consequently bring about fast fatigue of the tunnel insulating film of the relevant cell, so that the number of repeatable reprogramming actions in the chip is thereby determined. For example, in a silicon disk used for replacement of a hard disk, data is generally stored in each of individual sectors as a unit, and coupling data between the adjacent sectors is written in a specific area termed FAT (file allocation table). Since the content of such FAT needs to be reprogrammed every time data is written in any of the areas on the silicon disk, the FAT is subjected to the greatest electric stress derived from the reprogramming action, whereby its gate insulating film is deteriorated in the earliest stage. Thus, the service life of the silicon disk relative to reprogramming is determined virtually by the reprogramming life of the FAT.